XMEM+

The XMEM+ is a peripheral board which augments a standard Arduino / Genuino MEGA 2560 or MEGA ADK in two significant ways;

1. Increases the amount of available SRAM by 512K bytes
2. Adds true Parallel Bus Expansion capability

On-Board High-Speed logic assures that, except for the nineteen I/O pins dedicated to implement the eXternal MEMory interface, no other Arduino digital I/O signals are used. The external space appears seamlessly within the Arduino memory map and operates at full bus speed (no Wait-States).

512K byte External SRAM

A standard MEGA provides only 8,192 bytes of SRAM which must be divided amongst Stack, Heap, and Data purposes. As an Arduino program grows in complexity available SRAM can quickly dwindle. Low memory problems can be catastrophic and obvious or worse may appear as subtle errors and faulty operation occurring intermittently.

The XMEM+ increases Arduino MEGA SRAM by up to 512K bytes, organized as 16 banks of 32K byte each. The active 32KB bank follows the internal SRAM and resides in the MEGA memory space between addresses 0x2200 and 0xA1FF. All address and bank decoding is done by the On-board High-Speed logic. Simple software commands and routines help manage bank swapping.

The additional SRAM makes the MEGA much better suited and easier to use in applications requiring large amounts of fast memory such as buffering data before writing to an SD Card, servicing network communications, or creating and displaying graphical information.

Parallel Bus Expansion

Connecting parallel devices to a MEGA system has typically been accomplished through some form of "bit-banging" to emulate the necessary steps of Write and Read operations. This technique is less than ideal due to software overhead and reduced throughput.

Instead, the XMEM+ provides a fixed 23K byte Expansion Bus for connecting custom parallel type circuitry. Buffered ReaD, WRite, ENable, RESet OUT, 8-bit Data, and 16-bit Address signals are fully accessible for off-board prototyping.

The Expansion Bus is true Arduino MEGA memory space, inherently supporting all AVR software instructions and running at full system speed. Optional Wait-States can be inserted to accommodate slower parallel devices. In addition, the logic voltage for user circuitry attached to the Expansion Bus is jumper selectable to operate at either 3.3V or 5V levels.

Buffered SPI Signals

As an additional benefit, the MOSI and SCK Serial-Peripheral-Interface (SPI a.k.a. ICSP) signals are also routed through buffers. The ability to provide voltage translation between 5V and 3.3V is particularly handy when connecting to modern 3.3V only type SPI devices.